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W49F102 64K x 16 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W49F102 is a 1-megabit, 5-volt only CMOS flash memory organized as 64K x 16 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49F102 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
*
Single 5-volt operations: - 5-volt Read - 5-volt Erase - 5-volt Program
*
Low power consumption - Active current: 25 mA (typ.) - Standby current: 20 A (typ.)
* *
*
Fast Program operation: - Word-by-Word programming: 50 S (max.) Fast Erase operation: 100 mS (typ.) Fast Read access time: 45 nS Endurance: 10K cycles (typ.) Ten-year data retention Hardware data protection 8K word Boot Block with Lockout protection
* * * *
Automatic program and erase timing with internal VPP generation End of program or erase detection - Toggle bit - Data polling Latched address and data TTL compatible I/O JEDEC standard word-wide pinouts Available packages: 40-pin STSOP (10X14mm) and 44-pin PLCC
* * * * * *
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Publication Release Date: February 19, 2002 Revision A4
W49F102
PIN CONFIGURATIONS BLOCK DIAGRAM
VDD V SS
A9 A10 A11 A12 A13 A14 A15 NC #WE VDD NC #CE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33
40-pin STSOP
32 31 30 29 28 27 26 25 24 23 22 21
Vss A8 A7 A6 A5 A4 A3 A2 A1 A0 #OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Vss
#CE #OE #WE
CONTROL
DQ0
OUTPUT BUFFER . .
DQ15
A0
. .
A15
MAIN MEMORY DECODER (56K Words) BootBlock (8K Words)
V DDD# Q Q QC NN D 13 14 15 E C C D
6 5 4 3 2
# WN EC
AA 11 54
1 44 43 42 41 40 39 38 37 36
DQ12 DQ11 DQ10 DQ9 DQ8 Vss NC DQ7 DQ6 DQ5 DQ4
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A13 A12 A11 A10 A9 Vss NC A8 A7 A6 A5
PIN DESCRIPTION
SYMBOL A0 - A15 DQ0 - DQ15 #CE #OE #WE VDD VSS NC PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection
44-pin PLCC
35 34 33 32 31 30 29
DDDD QQQQ 3210
#NAA OC0 1 E
AAA 234
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W49F102
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W49F102 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for further details.
Boot Block Operation
There is one 8K-word boot block in this device, which can be used to store boot code. It is located in the first 8K words of the memory with the address range from 0000 hex to 1FFF hex. See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. Once the boot block programming lockout feature is activated, the chip erase function will only affect the main memory. In order to detect whether the boot block feature is set on the 8K-words block, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex". If the output data is "FF hex," the boot block programming lockout feature is activated; if the output data is "FE hex," the lockout feature is inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command sequence (or an alternate single-word command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-word command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed in a fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the main memory will be erased to FF(hex), and the data in the boot block will not be erased (remains same as before the chip erase operation). The entire memory array (main memory and boot block) will be erased to FF(hex) by the chip erase operation if the boot block programming lockout feature is not activated. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Main Memory Erase Operation
The main memory erase mode can be initiated by a six-word command sequence. After the command loading cycle, the device enters the internal main-memory erase mode, which is automatically timed and will be completed in a fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
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Publication Release Date: February 19, 2002 Revision A4
W49F102
Program Operation
The W49F102 is programmed on a word-by-word basis. Program operation can only change logical data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot block from "0" to "1" is needed before programming. The program operation is initiated by a 4-word command cycle (see Command Codes for Word Programming). The device will internally enter the program operation immediately after the wordprogram command is entered. The internal program timer will automatically time-out (50 S max. TBP) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49F102 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is less than 2.5V typical. (3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation.
Data Polling (DQ7 & DQ15)- Write Status Detection
The W49F102 includes a data polling feature to indicate the end of a program or erase cycle. When the W49F102 is in the internal program or erase cycle, any attempt to read DQ7 or DQ15 of the last word loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 or DQ15 will show the true data. Note that DQ7 or DQ15 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed.
Toggle Bit (DQ6 & DQ14)- Write Status Detection
In addition to data polling, the W49F102 provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 or DQ14 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code (00DAh). A read from address 0001H outputs the device code (002Fh). The product ID operation can be terminated by a three-word command sequence or an alternate one-word command sequence (see Command Definition table). In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE high, and raising A9 to 12 volts.
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W49F102
TABLE OF OPERATING MODES
Operating Mode Selection
(VHH = 12V 5%)
MODE #CE Read Write Standby Write Inhibit Output Disable Product ID VIL VIL VIH X X X VIL VIL #OE VIL VIH X VIL X VIH VIL VIL #WE VIH VIL X X VIH X VIH VIH AIN AIN X X X X
PINS ADDRESS Dout Din High Z High Z/DOUT High Z/DOUT High Z Manufacturer Code 00DA (Hex) DQ.
A0 = VIL; A1 - A15 = VIL; A9 = VHH
A0 = VIH; A1 - A15 = VIL; Device Code 002F (Hex) A9 = VHH
TABLE OF COMMAND DEFINITION
COMMAND DESCRIPTION Read Chip Erase Main Memory Erase Word Program Boot Block Lockout Product ID Entry Product ID Exit Product ID Exit
(1) (1)
No. of Cycles 1 6 6 4 6 3 3 1
1st Cycle Addr. Data AIN 5555 5555 5555 5555 5555 5555 XXXX DOUT AA AA AA AA AA AA F0
2nd Cycle Addr. Data
3rd Cycle Addr. Data
4th Cycle Addr. Data
5th Cycle Addr. Data
6th Cycle Addr. Data
2AAA 2AAA 2AAA 2AAA 2AAA 2AAA
55 55 55 55 55 55
5555 5555 5555 5555 5555 5555
80 80 A0 80 90 F0
5555 5555 AIN 5555
AA AA DIN AA
2AAA 2AAA
55 55
5555 5555
10 30
2AAA
55
5555
40
Note: Address Format: A14 - A0 (Hex); Data Format: DQ15 - DQ8 (Don't Care); DQ7 - DQ0 (Hex) Either one of the two Product ID Exit commands can be used.
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Publication Release Date: February 19, 2002 Revision A4
W49F102
Embedded Programming Algorithm
Start
Write Program Command Sequence (see below)
#Data Polling/ Toggle bit
Pause TBP
No Increment Address Last Address ? Yes Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
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W49F102
Embedded Erase Algorithm
Start
Write Erase Command Sequence (see below)
#Data Polling or Toggle BitSuccessfully Completed
Pause T EC /TSEC
Erasure Completed
Chip Erase Command Sequence (Address/Command):
Main Memory Erase Command Sequence (Address/Command): 5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
5555H/30H
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Publication Release Date: February 19, 2002 Revision A4
W49F102
Embedded #Data Polling Algorithm
Start
VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = Valid address equals any sector group address during chip erase
Read Byte (DQ0 - DQ7) Address = VA
No
DQ7 = Data ? Yes Pass
Embedded Toggle Bit Algorithm
Start
Read Byte (DQ0 - DQ7) Address = Don't Care
Yes DQ6 = Toggle ? No Pass
-8-
W49F102
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product Identification Entry (1)
Load data AA to address 5555
Product Identification and Boot Block Lockout Detection Mode (3)
Product Identification Exit (6)
Load data AA to address 5555 (2)
Load data 55 to address 2AAA
Read address = 00000 data = DA
Load data 55 to address 2AAA
Load data 90 to address 5555
Read address = 00001 data = 2F
(2)
Load data F0 to address 5555
(4) Pause 10 S
Read address = 00002 data = FF/FE
Pause 10 S
(5) Normal Mode
Notes for software product identification/boot block lockout detection: (1) Data Format: DQ15-DQ8 (Don't Care), DQ7 - DQ0 (Hex); Address Format: A14 - A0 (Hex) (2) A1 - A15 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.
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Publication Release Date: February 19, 2002 Revision A4
W49F102
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout Feature Set Flow
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 80 to address 5555
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 40 to address 5555
Pause 1 Sec.
Exit
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W49F102
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Except #OE Transient Voltage (<20 nS) on Any Pin to Ground Potential Voltage on #OE Pin to Ground Potential RATING -0.5 to +7.0 0 to +70 -65 to +150 -0.5 to VDD +1.0 -1.0 to VDD +1.0 -0.5 to 12.5 UNIT V C C V V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
DC Operating Characteristics
(VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C)
PARAMETER
SYM.
TEST CONDITIONS MIN.
LIMITS TYP. 25 MAX. 50
UNIT
Power Supply Current
ICC
#CE= #OE= VIL, #WE= VIH, all I/Os open Address inputs = VIL/VIH, at f = 5 MHz
-
mA
Standby VDD Current (TTL input) Standby VDD Current (CMOS input)
ISB1 #CE = VIH, all I/Os open Other inputs = VIL/VIH ISB2 #CE = VDD -0.3V, all I/Os open Other inputs = VDD -0.3V/ Vss VIN = Vss to VDD VOUT = Vss to VDD IOL = 2.1 mA
-0.3 2.0 2.4
2 20 -
3 100 10 10 0.8 VDD +0.5 0.45 -
mA A A A V V V V
Input Leakage Current ILI Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage ILO VIL VIH VOL
VOH IOH = -0.4 mA
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Publication Release Date: February 19, 2002 Revision A4
W49F102
Power-up Timing
PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU. READ TPU. WRITE TYPICAL 100 5 UNIT S mS
CAPACITANCE
(VDD = 5.0V, TA = 25 C, f = 1 MHz)
PARAMETER I/O Pin Capacitance Input Capacitance
SYMBOL CI/O CIN
CONDITIONS VI/O = 0V VIN = 0V
MAX. 12 6
UNIT pF pF
AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 3.0V <5 nS 1.5V/1.5V 1 TTL Gate and CL = 30 pF CONDITIONS
AC Test Load and Waveform
+5V
1.8K
DOUT
30 pF (Including Jig and Scope)
1.3K
Input
3V 1.5V 0V Test Point
Output
1.5V
Test Point
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W49F102
AC Characteristics, continued
Read Cycle Timing Parameters
(VDD = 5.0V 5 % for 35 nS; VDD = 5.0V 10 % for 45 nS, VSS = 0V, TA = 0 to 70 C)
PARAMETER
SYMBOL
W49F102-45 MIN. MAX. 45 45 25 20 20 -
UNIT
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time #CE Low to Active Output #OE Low to Active Output #CE High to High-Z Output #OE High to High-Z Output Output Hold from Address Change
TRC TCE TAA TOE TCLZ TOLZ TCHZ TOHZ TOH
45 0 0 0
nS nS nS nS nS nS nS nS nS
Write Cycle Timing Parameters
PARAMETER Address Setup Time Address Hold Time #WE and #CE Setup Time #WE and #CE Hold Time #OE High Setup Time #OE High Hold Time #CE Pulse Width #CE High Width #WE Pulse Width #WE High Width Data Setup Time Data Hold Time Word Programming Time Erase Cycle Time SYMBOL TAS TAH TCS TCH TOES TOEH TCP TPH TWP TWPH TDS TDH TBP TEC MIN. 0 45 0 0 0 0 50 50 45 45 45 0 TYP. 10 0.1 MAX. 50 1 UNIT nS nS nS nS nS nS nS nS nS nS nS nS S Sec.
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
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Publication Release Date: February 19, 2002 Revision A4
W49F102
AC Characteristics, continued
Data Polling and Toggle Bit Timing Parameters
PARAMETER SYMBOL W49F102-45 MIN. #OE to Data Polling Output Delay #CE to Data Polling Output Delay #OE to Toggle Bit Output Delay #CE to Toggle Bit Output Delay TOEP TCEP TOET TCET MAX. 25 45 25 45 nS nS nS nS UNIT
TIMING WAVEFORMS
Read Cycle Timing Diagram
T RC Address A15-0 TCE #CE
#OE
TOE
VIH #WE
TOLZ
TOHZ
TCLZ High-Z DQ15-0
T OH Data Valid TAA
TCHZ High-Z Data Valid
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W49F102
Timing Waveforms, continued
#WE Controlled Command Write Cycle Timing Diagram
TAS Address A15-0
TAH
#CE
TCS TOES
TCH TOEH
#OE TWP TWPH
#WE
TDS DQ15-0 Data Valid
TDH
#CE Controlled Command Write Cycle Timing Diagram
TAS
TAH
Address A15-0 TCPH TCP #CE TOES #OE TOEH
#WE TDS DQ15-0 High Z Data Valid
TDH
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Publication Release Date: February 19, 2002 Revision A4
W49F102
Timing Waveforms, continued
Program Cycle Timing Diagram
Word Program Cycle Address A15-0 5555 2AAA 5555 Address
DQ15-0
XXAA
XX55
XXA0
Data-In
#CE
#OE TWP #WE Word 0
TWPH
TBP
Word 1
Word 2
Word 3
Internal Write Start
#DATA Polling Timing Diagram
Address A15-0 #WE TCEP #CE TOEH #OE TOEP DQ7/DQ15 X X TBP or TEC X X TOES
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W49F102
Timing Waveforms, continued
Toggle Bit Timing Diagram
Address A15-0
#WE
#CE TOEH #OE TOES
DQ6/DQ14 TBP or EC T
Boot Block Lockout Enable Timing Diagram
Six-word code for Boot Block Lockout Feature Enable Address A15-0 5555 2AAA 5555 5555 2AAA 5555
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX40
#CE
#OE #WE
TWP TWPH SW0 SW1 SW23 SW3 SW4 SW5
TWC
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Publication Release Date: February 19, 2002 Revision A4
W49F102
Timing Waveforms, continued
Chip Erase Timing Diagram
Six-word code for 5V-only software chip erase Address A15-0 5555 2AAA 5555 5555 2AAA 5555
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
#CE
#OE #WE
TWP TWPH SW0 SW1 SW2 SW3 SW4 SW5
TEC
Internal Erase starts
Main Memory Erase Timing Diagram
Six-word code for 5V-only software Main Memory Erase Address A15-0 5555 2AAA 5555 5555 2AAA 5555
DQ15-0 #CE
XXAA
XX55
XX80
XXAA
XX55
XX30
#OE #WE
TWP TWPH SW0 SW1 SW2 SW3 SW4 SW5
TEC
Internal Erase starts
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W49F102
ORDERING INFORMATION
PART NO. ACCESS POWER SUPPLY STANDBY VDD CURRENT TIME CURRENT MAX. (nS) (mA) MAX. (A) 45 45 50 50 100 (CMOS) 100 (CMOS) PACKAGE CYCLE
W49F102Q-45 W49F102P-45
Notes:
40-pin STSOP (10 mm x 14 mm) 44-pin PLCC
10K 10K
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
HOW TO READ THE TOP MARKING
Example: The top marking of 44-pin PLCC W49F102P-45
W49F102P-45 2138977A-A12 149OBSA
1 line: winbond logo 2 line: the part number: W49F102P-45 3 line: the lot number 4 line: the tracking code: 149 O B SA 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ...etc. B: IC revision; A means version A, B means version B, ...etc. SA: Process code
th rd nd st
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Publication Release Date: February 19, 2002 Revision A4
W49F102
PACKAGE DIMENSIONS
44-pin PLCC
HD D
6 1 44 40
Dimension in Inches
Dimension in mm
Symbol
7 39
Min. Nom. Max. Min. Nom. Max.
0.185 0.020 0.145 0.150 0.155 0.026 0.028 0.032 0.016 0.018 0.022 0.008 0.010 0.014 0.51 3.68 0.66 0.41 0.20 3.81 0.71 0.46 0.25 3.94 0.81 0.56 0.36 4.70
E HE
GE
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 1.27 BSC 0.050 BSC 0.590 0.610 0.630 14.99 15.49 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 0.004 2.29 2.54 2.79 0.10
L A2 A
Seating Plane
e
GD
b b1
A1 y
1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
40-pin STSOP (10 mm x 14 mm)
HD
Dimension in Inches Dimension in mm Min. Nom. Max. 1.20 0.05 0.95 0.17 0.10 1.00 0.22 0.15 0.15 1.05 0.27 0.20 12.50 10.10 14.20
D
Symbol
Min.
Nom. Max. 0.047
c
e1
M
A A1 A2 b c D E HD e L L1 Y
0.002 0.037 0.007 0.004
0.006 0.039 0.041 0.009 0.011 0.006 0.008
E
0.10(0.004)
b
0.484 0.488 0.492 0.390 0.394 0.398 0.543
12.30 12.40 9.90 10
0.551 0.559 13.80 14.00 0.020 0.50 0.028 0.50 0.60 0.8 0.004 3 5 0.00 0 3
0.020
0.024 0.031
0.70
A L L1 A2 A1
0.000 0
0.10 5
Y
Controlling dimension: Millimeters
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W49F102
VERSION HISTORY
VERSION A1 A2 A3 DATE Jun. 1999 Oct. 1999 12/21/1999 PAGE 13 Initial Issued Change Read Cycle Timing Parameter: VDD = 5.0V 10% for 40, 45, 50, 55, 70 nS Trc: 35 nS->40 nS; 40 nS->42 nS Tah: 50 nS->45 nS Twp & Twph: 90 nS->45 nS Tcp: 90 nS->50 nS Add in Tcph = 50 nS Tds: 50 nS->45 nS 1,21 A4 Feb. 19, 2002 1, 13, 14, 19 1, 2, 20, 21 4 6, 7, 8 17 19 Delete 1K cycling option Delete read access time of 40 nS Rename TSOP (10 x 14 mm) as STSOP (10 x 14 mm) Modify VDD Power Up/Down Detection in Hardware Data Protection Delete old flow chart and add embedded algorithm Modify Program Cycle Timing Diagram Add HOW TO READ THE TOP MARKING Correct the example of HOW TO READ THE TOP MARKING Correct the Part. No for ordering information DESCRIPTION
1, 11, 13, 14, 19 Delete 35, 50, 55, 70 nS bins 13
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: February 19, 2002 Revision A4

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